Research papers on computer architecture

Name / given name / last name / within your computer architecture letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware e influence g cpu voltage noise through electromagnetic ias oct 25 00:00:00 edt 2017 wed oct 25 00:00:00 edt replacement policy based on expected hit ad-reza ad oct 17 00:00:00 edt 2017 tue oct 17 00:00:00 edt ging hardware caches for oct 12 00:00:00 edt 2017 thu oct 12 00:00:00 edt -stage cpi oct 10 00:00:00 edt 2017 tue oct 10 00:00:00 edt -based simulation sep 25 00:00:00 edt 2017 mon sep 25 00:00:00 edt all latest 5-gpu: a heterogeneous cpu-gpu may 19 00:00:00 edt 2017 fri may 19 00:00:00 edt m: an efficient cache coherence mechanism for jun 20 00:00:00 edt 2017 tue jun 20 00:00:00 edt s: bit-serial deep neural network jun 16 00:00:00 edt 2017 fri jun 16 00:00:00 edt zing read-once data flow in big-data jun 16 00:00:00 edt 2017 fri jun 16 00:00:00 edt ent in-memory processing using sep 11 00:00:00 edt 2017 mon sep 11 00:00:00 edt all popular sion author digital your ical & computer engineering. An efficient cache coherence mechanism for ation year: 2017, page(s):46 - sing-in-memory (pim) architectures cannot use traditional approaches to cache coherence due to the high off-chip traffic consumed by coherence messages. The hybrid memory cube (hmc) isa type of 3d-stacked dram that has drawn great attention because of its usability for server systems and processing-in-memory (pim) architecture.

A heterogeneous cpu-fpga ation year: 2017, page(s):38 - geneous computing is a promising direction to address the challenges of performance and power walls in high-performance computing, where cpu-fpga architectures are particularly promising for application acceleration. However, the development of such architectures associated with optimal memory hierarchies is challenging due to the absence of an integrated simulator to support full system sim... Efficient accelerator design for neural networks using computation ation year: 2017, page(s):72 - ations of neural networks in various fields of research and technology have expanded widely in recent years.

An architecture for accelerated processing near ation year: 2015, page(s):26 - ing energy efficiency is crucial for both mobile and high-performance computing systems while a large fraction of total energy is consumed to transfer data between storage and processing units. The impact of memory errors on application  ation year: 2017, page(s):51 - reliability is a key factor in the design of warehouse-scale computers. Of performance unfairness in numa system ation year: 2017, page(s):26 - (non-uniform memory access) system architectures are commonly used in high-performance computing and datacenters.

Within each architecture, a processor-interconnect is used for communication between the different sockets and examples of such interconnect include intel qpi and amd hypertransport. Energy-efficient processor architecture for embedded ation year: 2008, page(s):29 - present an efficient programmable architecture for compute-intensive embedded applications. The processor architecture uses instruction registers to reduce the cost of delivering instructions, and a hierarchical and distributed data register organization to deliver data.

Coarse-grained reconfigurable architecture for compute-intensive mapreduce ation year: 2016, page(s):69 - -scale workloads often show parallelism of different levels. Although processors such as gpgpus and fpgas show good performance of speedup, there is still vacancy for a low power, high efficiency and dynamically reconfigurable one, and coarse-grained reconfigurable architecture (cgra) seems to be one possible choice. However, commonly used cloud computing server workloads are not well-represented by the spec integer and floating-point benchmark and parsec suites typically used by the computer architecture community.

Aware roofline model: upgrading the ation year: 2014, page(s):21 - roofline model graphically represents the attainable upper bound performance of a computer architecture. This paper analyzes the original roofline model and proposes a novel approach to provide a more insightful performance modeling of modern architectures by introducing cache-awareness, thus significantly improving the guidelines for application optimization. If a stochastic representation is used to implement a programmable general-purpose architecture akin to cpus...

Gpu architecture for memory-unaware gpu ation year: 2014, page(s):101 - mmer-managed gpu memory is a major challenge in writing gpu applications. We define a unified model describing a superposition of the two architectures, and use it to identify operation zones for which each machine is more suitable. A technique for extending lifetime of sram-nvm hybrid ation year: 2015, page(s):115 - ly, researchers have explored way-based hybrid sram-nvm (non-volatile memory) last level caches (llcs) to bring the best of sram and nvm together.

Modeling solid state drives for holistic system ation year: 2017, page(s):Existing solid state drive (ssd) simulators unfortunately lack hardware and/or software architecture models, and consequently are far from capturing the critical features of contemporary ssd devices. Fpga-based in-line accelerator for ation year: 2014, page(s):57 - present a method for accelerating server applications using a hybrid cpu+fpga architecture and demonstrate its advantages by accelerating memcached, a distributed key-value system. Characters computer architecture letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware ical & computer engineering.

Mail: sorin@ your about this e influence computer architecture letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ilp processors,  workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, i/o architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques,  domain-specific processor architectures (e. Real-time and high-availability architectures, reconfigurable is a semi-annual forum for fast publication of new, high-quality ideas in the form of short, critically refereed, technical papers.

Members of the technical committee on computer architecture will receive the print issue as a benefit of being a member. And subscriptions er architecture, ieee computer society technical committee ieee computer society technical committee on computer architecture (tcca) is involved with research and development in the integrated hardware and software design of general- and special-purpose uniprocessors and parallel computers. Tcca annually sponsors/cosponsors the international symposium on computer architecture, and with the acm sigarch, it jointly administers the eckert-mauchly award for contributions to computer architecture.

Tcca also helps organize special issues of society periodicals and publishes a newsletter periodically, which contains meeting reports, abstracts of technical reports, calls for papers, and other er architecture, ieee computer society technical committee format to view format is only available to ieee members.